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91400 rm (im) hk-1/20 ver.2.02 22599 preliminary overview the lc865632a/28a/24a/20a/16a/12a/08a microcontrollers are 8-bit single chip microcontrollers with the following on-chip functional blocks : - cpu : operable at a minimum bus cycle time of 0.5s (microsecond) - on-chip rom maximum capacity : 32k bytes - on-chip ram capacity : 640 bytes (lc865632a/28a/24a) : 512 bytes (lc865620a/16a/12a/08a) - 16-bit timer/counter (or two 8-bit timers) - 16-bit timer/ pwm (or two 8-bit timers) - 8-channel 8-bit ad converter - two 8-bit synchronous serial-interface circuits - 13-source 10-vectored interrupt system all of the above functions are fabricated on a single chip. features (1) read only memory (rom) : lc865632a 32512 8 bits : lc865628a 28672 8 bits : lc865624a 24576 8 bits : lc865620a 20480 8 bits : lc865616a 16384 8 bits : lc865612a 12288 8 bits : LC865608A 8192 8 bits (2) random access memory (ram) : lc865632a/28a/24a 640 8 bits : lc865620a/16a/12a/08a 512 8 bits (3) bus cycle time / instruction cycle time the lc865632a/28a/24a/20a/16a/12a/08a are constructed to read rom twice within one instruction cycle. it has 1.7 times more performance capability within the same instruction cycle compared to our 4-bit microcontrollers (lc66000 series). bus cycle time indicates the speed to read rom. bus cycle time cycle time system clock oscillation oscillation frequency voltage 0.5 s 1.0 s ceramic resonator oscillation 6mhz 4.5 - 6.0v 2.0 s 4.0 s ceramic resonator oscillation 1.5mhz 2.5 - 6.0v 3.75 s 7.5 s rc resonator oscillation 800mhz 2.5 - 6.0v 91.5 s 183 s crystal oscillation 32.568khz 2.5 - 6.0v 8-bit single chip microcontrolle r lc865632/28/24/20/16/12/08a ordering number : enn*6698 cmos ic
lc865632/28/24/20/16/12/08a 2/20 (4) ports - input / output ports : 6 ports (42 terminals) input/output port programmable in nibble units : 1 port (8 terminals) (when the n-channel open drain output is selected, the data in a bit can be inputted.) input/output port programmable in a bit : 5 ports (34 terminals) include 15v withstand n-channel open drain output port : 3 ports (18 terminals) - input ports : 2 ports (13 terminals) (5) ad converter - 8 channels 8-bit ad converters (6) serial-interface - two 8-bit serial-interface circuits lsb first / msb first function available - internal 8-bit baud-rate generator in common with two serial-interface circuits (7) timers - timer0 16-bit timer / counter 2-bit prescaler + 8-bit programmable prescaler mode 0 : two 8-bit timers with programmable prescaler mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter mode 2 : 16-bit timer with a programmable prescaler mode 3 : 16-bit counter the resolution of timer is 1 tcyc. (tcyc : cycle time) - timer 1 16-bit timer / pwm mode 0 : two 8-bit timers mode 1 : 8-bit timer + 8-bit pwm mode 2 : 16-bit timer mode 3 : variable-bit pwm (9-16 bits) in mode 0 and mode 1, the resolution of timer and pwm is tcyc. in mode 2 and mode 3, the resolution of timer and pwm selectable ; tcyc or 1/2tcyc by program - base timer every 500ms overflow system for a clock application (using 32.568khz crystal oscillation for base timer clock) every 976 s, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.568khz crystal oscillation for base timer clock) the base timer clock selectable ; 32.568khz crystal oscillation, system clock, and programmable prescaler output of timer 0 (8) buzzer output - the buzzer sound frequency selectable ; 4khz, 2khz (using 32.568khz crystal oscillation for base timer clock) (9) remote control receiver circuit (shares with the p73/int3/t0in terminal) - noise rejection function - switch polarity function (10) watchdog timer - the watchdog timer is taken on rc outside - watchdog timer operation selectable : interrupt system, system reset
lc865632/28/24/20/16/12/08a 3/20 (11) interrupts system - 13-sources 10-vectored interrupts : 1. external interrupt int0 (include watchdog timer) 2. external interrupt int1 3. external interrupt int2, timer / counter t0l (lower 8 bits) 4. external interrupt int3, base timer 5. timer / counter t0h (upper 8-bit) 6. timer t1l, timer t1h 7. serial interface sio0 8. serial interface sio1 9. ad converter 10. port 0 - built-in interrupt priority control register microcontroller allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. it can specify a low level or a high level interrupt priority from int2/t0l through port 0 (i.e. the above interrupt number from three through ten). it can also specify a low level or the highest level interrupt priority to int0 and int1. (12) real-time service operation the real-time service (rts) functions the 4-byte data-transfer between the special function registers at acknowledging the interrupt request. the rts starts within 1 instruction cycle-time and completes within 5 instructions cycle-time after occurring the interrupt request. (13) sub-routine stack levels - 128 levels (max.) : stack area included in ram area (14) multiplication and division - 16 bits 8-bit (7 instruction cycle times) - 16 bits 8-bit (7 instruction cycle times) (15) three oscillation circuits - on-chip rc oscillation circuit using for the system clock - on-chip cr oscillation circuit using for the system clock - on-chip crystal oscillation circuit using for the system clock and for time-base clock xt1 terminal can be used as p74 (16) standby function - halt mode function the halt mode is used to reduce the power dissipation. in this operation mode, the program execution is stopped. this operation mode can be released by the interrupt request signals or the initial system reset request signal. - hold mode function the hold mode is used to freeze all the oscillations ; rc (internal), cf and crystal oscillations. this mode can be released by the following operations. reset terminal ( res ) set to low level p70/int0, p71/int1 terminals set to assigned level (programmable) input a port 0 interrupt condition (17) factory shipment dip64s, qfp64e delivery form (18) development support tools - evaluation (eva) chip : lc866098 - eprom version : lc86e5632 - one time version : lc86p5632 - emulator : eva86000 + ecb866600 (evaluation chip board) + pod865000 (pod for dip64s) + pod865010 (pod for qfp64e)
lc865632/28/24/20/16/12/08a 4/20 pin assignment dip64s package dimension (unit : mm) 3071 sanyo : dip-64s(750mil) p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/buz p17/pwm test1 res xt1/p74 xt2 vss cf1 cf2 vdd p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 p70/int0 p71/int1 p72/int2/t0in p73/int3/t0in p30 p31 p32 p33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p07 p06 p05 p04 p03 p02 p01 p00 p27 p26 p25 p24 p23 p22 p21 p20 vddvpp vss p51 p50 p47 p46 p45 p44 p43 p42 p41 p40 p37 p36 p35 p34
lc865632/28/24/20/16/12/08a 5/20 qip64e package dimension (unit : mm) 3159 sanyo : qip-64e test1 res xt1/p74 xt2 vss cf1 cf2 vdd p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 p27 p26 p25 p24 p23 p22 p21 p20 vddvpp vss p51 p50 p47 p46 p45 p44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p70/int0 p71/int1 p72/int2/t0in p73/int3/t0in p30 p31 p32 p33 p34 p35 p36 p37 p40 p41 p42 p43 p17/pwm p16/buz p15/sck1 p14/si1/sb1 p13/so1 p12/sck0 p11/si0/sb0 p10/so0 p07 p06 p05 p04 p03 p02 p01 p00
lc865632/28/24/20/16/12/08a 6/20 system block diagram interrupt control standby control ir rom pla cf rc x?tal clock generator pc base timer sio0 sio1 timer 0 timer 1 adc int0 to 3 noise filtter ram (128 bytes) port 1 port 7 port 8 port 2 port 3 port 5 port 4 bus interface acc b register c register psw rar ram stack pointer watchdog timer port 0 real time service alu
lc865632/28/24/20/16/12/08a 7/20 pin description pin name i/o function description option vss - power pin (?) - vdd - power pin (+) - vddvpp * - power pin (+) - port0 p00 - p07 i/o 8-bit input/output port input for port 0 interrupt input/output in nibble units input for hold release pull-up resistor : provided/not provided output form : cmos/n-channel open drain port1 p10 - p17 i/o 8-bit input/output port input/output can be specified in bit unit other pin functions p10 sio0 data output p11 sio0 data input/bus input/output p12 sio0 clock input/output p13 sio1 data output p14 sio1 data input/bus input/output p15 sio1 clock input/output p16 buzzer output p17 timer1 output (pwm output) output form : cmos/n-channel open drain port2 p20 - p27 i/o 8-bit input/output port input/output in bit unit output form : cmos/n-channel open drain port3 p30 - p37 i/o 8-bit input/output port input/output in bit unit 15v withstand at n-channel open drain output pull-up resistor : provided/not provided output form : cmos/n-channel open drain port4 p40 - p47 i/o 8-bit input/output port input/output in bit unit 15v withstand at n-channel open drain output pull-up resistor : provided/not provided output form : cmos/n-channel open drain port5 p50, p51 i/o 2-bit input/output port input/output in bit unit 15v withstand at n-channel open drain output pull-up resistor : provided/not provided output form : cmos/n-channel open drain * connect like the following figure to reduce noise into a vdd terminal. short-circuit the vdd terminal to the vddvpp terminal. short-circuit the vss terminal to the vss terminal. lsi vdd vddvpp vss vss power supply
lc865632/28/24/20/16/12/08a 8/20 pin name i/o function description option 5-bit input port other pin functions p70 : int0 input/hold release/n-channel tr. output for watchdog timer p71 : int1 input/hold release input p72 : int2 input/timer 0 event input p73 : int3 input with noise filter/timer 0 event input p74 : input pin xt1 for 32.768khz crystal oscillation interrupt received form, vector address pull-up resistor : provided/not provided (p70,71,72,73) p74 does not have pull-up resistor option rising falling rising & falling high level low level vector int0 enable enable disable enable enable 03h int1 enable enable disable enable enable 0bh int2 enable enable enable disable disable 13h port7 p70 p71 - p74 i/o i int3 enable enable enable disable disable 1bh port8 p80 - p87 i 8-bit input port pin description ad input port (8 port pins) - res i reset pin - test1 o test pin should be left unconnected output fixed high xt1/ p74 i input pin for 32.768khz crystal oscillation in case of non use, connect to vdd other function : input port p74 - xt2 o output pin for 32.768khz crystal oscillation in case of non use, should be left unconnected - cf1 i input pin for ceramic resonator oscillation - cf2 o output pin for ceramic resonator oscillation - * all of port options can be specified in bit unit. * a state of pins at reset pin name input/output mode a state of pull-up resistor specified at pull-up option port 0 ports 70,71,72,73 input fixed pull-up resistor exist ports 1,2,3,4,5 input programmable pull-up resistor off
lc865632/28/24/20/16/12/08a 9/20 1. absolute maximum ratings at vss=0v and ta=25 c ratings parameter symbol pins conditions v dd[v] min. typ. max. unit supply voltage vddmax vdd,vddvpp vdd=vddvpp -0.3 +7.0 input voltage vi(1) ports 71,72,73, 74 port 8 res -0.3 vdd+0.3 vio(1) ports 0,1,2 ports 3,4,5 at cmos output option -0.3 vdd+0.3 input/output voltage vio(2) ports 3,4,5 at n-ch open drain output option -0.3 15 v peak output current ioph(1) ports 0,1,2,3,4,5 cmos output at each pin -4 ioah(1) ports 0,1 total all pins -20 high level output current total output current ioah(2) ports 2,3,4,5 total all pins -20 iopl(1) ports 0,1,2,3,4,5 at each pin 20 peak output current iopl(2) port 70 at each pin 15 ioal(1) ports 0,1 port 70 total all pins 40 ioal(2) port 2 total all pins 40 low level output current total output current ioal(3) ports 3,4,5 total all pins 80 ma pdmax(1) dip64s ta=-30 to +70 c 670 maximum power dissipation pdmax(2) qfp64e ta=-30 to +70 c 420 mw operating temperature range topr -30 +70 storage temperature range tstg -65 +150 c
lc865632/28/24/20/16/12/08a 10/20 2. recommended operating range at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit vdd(1) 0.98 s tcyc 400 s 4.5 6.0 operating supply voltage range vdd(2) vdd 3.9 s tcyc 400 s 2.5 6.0 hold voltage vhd vdd rams and the registers hold voltage at hold mode. 2.0 6.0 vih(1) port 0 (schmitt) output disable 2.5-6.0 0.4vdd +0.9 vdd vih(2) ports 1,2 ports 72,73 (schmitt) output disable 2.5-6.0 0.75vdd vdd vih(3) port 70 (port input/interrupt) port 71 res (schmitt) output n-channel tr. off 2.5-6.0 0.75vdd vdd vih(4) port 70 (watchdog timer) output n-channel tr. off 2.5-6.0 0.9vdd vdd vih(5) port 74 port 8 output n-channel tr. off 2.7-6.0 0.75vdd vdd 4.0-6.0 0.75vdd vdd vih(6) ports 3,4,5 of cmos output output disable 2.5-4.0 0.8vdd vdd 4.0-6.0 0.75vdd 13.5 input high voltage vih(7) ports 3,4,5 of open drain output output disable 2.5-4.0 0. 8vdd 13.5 vil(1) port 0 (schmitt) output disable 2.5-6.0 vss 0.2vdd vil(2) ports 1,2,3,4,5 ports 72,73 (schmitt) output disable 2.5-6.0 vss 0.25vdd vil(3) port 70 (port input/interrupt) port 71 res (schmitt) n-channel tr. off 2.5-6.0 vss 0.25vdd vil(4) port 70 (watchdog timer) n-channel tr. off 2.5-6.0 vss 0.8vdd -1.0 input low voltage vil(5) port 74 port 8 output n-channel tr. off 2.5-6.0 vss 0.25vdd v 4.5-6.0 0.98 400 operation cycle time tcyc 2.5-6.0 3.9 400 s continue.
lc865632/28/24/20/16/12/08a 11/20 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit fmcf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 1 4.5-6.0 6 fmcf(2) cf1, cf2 1.5mhz (ceramic resonator oscillation) refer to figure 1 2.5-6.0 1.5 fmrc rc oscillation 2.5-6.0 0.3 0.8 3.0 mhz oscillation frequency range (note 1) fsxtal xt1, xt2 32.768khz (crystal oscillation) refer to figure 2 2.5-6.0 32.768 khz tmscf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 3 4.5-6.0 4.5-6.0 tmscf(2) cf1, cf2 1.5mhz (ceramic resonator oscillation) refer to figure 3 2.5-6.0 ms 4.5-6.0 oscillation stabilizing time period (note 1) tssxtal xt1, xt2 32.768khz (crystal oscillation) refer to figure 3 2.5-6.0 s (note 1) the oscillation constant is shown on table 1 and table 2.
lc865632/28/24/20/16/12/08a 12/20 3. electrical characteristics at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) ports 3,4,5 of open drain output output disable vin=13.5v (including the off- leak current of the output tr.) 2.5-6.0 5 iih(2) port 0 without pull-up mos tr. ports 1,2,3,4,5 output disable pull-up mos tr. off. vin=vdd (including the off- leak current of the output tr.) 2.5-6.0 1 iih(3) ports 70,71,72,73 without pull-up mos tr. port 8 vin=vdd 2.5-6.0 1 input high current iih(4) res vin=vdd 2.5-6.0 1 iil(1) ports 1,2,3,4,5 port 0 without pull-up mos tr. output disable pull-up mos tr. off. vin=vss (including the off- leak current of the output tr.) 2.5-6.0 -1 iil(2) ports 70,71,72,73 without pull-up mos tr. port 8 vin=vss 2.5-6.0 -1 input low current iil(3) res vin=vss 2.5-6.0 -1 a voh(1) ioh=-1.0ma 4.5-6.0 vdd-1 output high voltage voh(2) ports 0,1,2,3,4,5 of cmos output ioh=-0.1ma 2.5-6.0 vdd-0.5 vol(1) iol=10ma 4.5-6.0 1.5 vol(2) iol=1.6ma 4.5-6.0 0.4 vol(3) ports 0,1,2,3,4,5 iol=1.0ma the current of any unmeasurement pin is not over 1 ma. 2.5-6.0 0.4 vol(4) iol=1ma 4.5-6.0 0.4 output low voltage vol(5) port 70 iol=0.5ma 2.5-6.0 0.4 v 4.5-6.0 15 40 70 pull-up mos tr. resistor rpu ports 0,1,2,3,4,5 ports 70,71,72,73 voh=0.9vdd 2.5-4.5 25 70 150 k ? hysteresis voltage vhis ports 0,1,2,3,4,5 ports 70,71,72,73 res output disable 2.5-6.0 0.1vdd v pin capacitance cp all pins f=1mhz unmeasurement terminals for the input are set to vss level. ta=25 c 2.5-6.0 10 pf
lc865632/28/24/20/16/12/08a 13/20 4. serial input/output characteristics at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit cycle tckcy(1) 2.7-6.0 2 low level pulse width tckl(1) 2.7-6.0 1 input clock high level pulse width tckh(1) sck0, sck1 refer to figure 5. 2.7-6.0 1 cycle tckcy(2) 2.7-6.0 2 low level pulse width tckl(2) 2.7-6.0 1/2 tckcy serial clock output clock high level pulse width tckh(2) sck0, sck1 use pull-up resistor (1k ? ) when open drain output. refer to figure 5. 2.7-6.0 1/2 tckcy tcyc 4.5-6.0 0.1 data set up time tick 2.7-6.0 0.4 4.5-6.0 0.1 serial input data hold time tcki si0,si1 sb0,sb1 data set-up to sck0,1 data hold from sck0,1 refer to figure 5. 2.7-6.0 0.4 4.5-6.0 7/12 tcyc +0.2 output delay time (serial clock is external clock) tcko(1) 2.7-6.0 7/12 tcyc +1 4.5-6.0 1/3 tcyc +0.2 serial output output delay time (serial clock is internal clock) tcko(2) so0,so1 sb0,sb1 use pull-up resistor (1k ? ) when open drain output. data hold from sck0,1 refer to figure 5. 2.7-6.0 1/3 tcyc +1 s
lc865632/28/24/20/16/12/08a 14/20 5. pulse input conditions at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0, int1 int2/t0in int3 interrupt acceptable timer0-countable 2.7-6.0 1 tpih(2) tpil(2) int3/t0in (the noise rejection clock is selected to 1/1.) interrupt acceptable 2.7-6.0 2 tpih(3) tpil(3) int3/t0in (the noise rejection clock is selected to 1/16.) interrupt acceptable 2.7-6.0 32 tcyc high/low level pulse width tpil(4) res reset acceptable 4.5-6.0 200 s 6. ad converter characteristics at ta=-30 c to + 70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 4.5-6.0 8 bit absolute precision (note 2) et 4.5-6.0 1.5 lsb ad conversion time = 16 tcyc (adcr2=0) (note 3) 15. 68 (tcyc= 0.98 s) 65.28 (tcyc= 4.08 s) conversion time tcad ad conversion time = 32 tcyc (adcr2=1) (note 3) 4.5-6.0 31.36 (tcyc= 0.98 s) 130.56 (tcyc= 4.08 s) s analog input voltage range vain 4.5-6.0 vss vdd v iainh vain=vdd 4.5-6.0 1 analog port input current iainl an0 - an7 vain=vss 4.5-6.0 -1 a (note 2) absolute precision excepts quantizing error (1/2 lsb). (note 3) the conversion time means the time from executing the ad conversion instruction to setting the complete digital conversion value to the register.
lc865632/28/24/20/16/12/08a 15/20 7. current dissipation characteristics at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddop(1) fmcf=6mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 4.5-6.0 10 20 iddop(2) 4.5-6.0 3 7 iddop(3) fmcf=1.5mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 2.7-4.5 1.5 5 iddop(4) 4.5-6.0 1.0 3.5 iddop(5) fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscillation 2.7-4.5 0.6 3.0 ma iddop(6) 4.5-6.0 50 150 current dissipation during basic operation (note 4) iddop(7) vdd fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : crystal oscillation internal rc oscillation stops 2.7-4.5 25 75 a continue.
lc865632/28/24/20/16/12/08a 16/20 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddhalt(1) halt mode fmcf=6mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 4.5-6.0 5 10 iddhalt(2) 4.5-6.0 2.2 4.6 iddhalt(3) halt mode fmcf=1.5mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 2.7-4.5 0.8 2.5 ma iddhalt(4) 4.5-6.0 800 2000 iddhalt(5) halt mode fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscillation 2.7-4.5 400 1500 iddhalt(6) 4.5-6.0 35 140 current dissipation in halt mode (note 4) iddhalt(7) vdd halt mode fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : crystal oscillation internal rc oscillation stops 2.7-4.5 11 56 iddhold(1) 4.5-6.0 0.05 30 current dissipation in hold mode (note 4) iddhold(2) vdd hold mode 2.7-4.5 0.02 20 a (note 4) the currents of the output transistors and the pull-up mos transistors are ignored.
lc865632/28/24/20/16/12/08a 17/20 table 1. ceramic resonator oscillation recommended constant (main clock) oscillation type maker oscillator c1 c2 rf rd csa12.0mtz 33pf 33pf open 560 ? csa12.0mtz 39pf 30pf open 0 ? 12mhz ceramic resonator oscillation murata cst12.0mtw on chip open 560 ? csa3.00mg040 100pf 100pf open 1.5 ? 3mhz ceramic resonator oscillation murata cst3.00mgw040 on chip open 1.5 ? * both c1 and c2 must use k rank (10%) and sl characteristics. table 2. crystal oscillation recommended constant (sub clock) oscillation type maker oscillator c3 c4 kyocera kf-38g-13p0200 18pf 18pf 32.768khz crystal oscillation seiko epson mc-306,c-002rx,32.768khz 4pf 4pf * both c3 and c4 must use j rank (5%) and ch characteristics. (it is about the application which is not in need of high precision. use k rank (10%) and sl characteristics.) (notes) since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. figure 1 main-clock circuit figure 2 sub-clock circuit ceramic oscillation circuit crystal oscillation cf1 cf2 rf rd c2 cf c1 xt1 xt2 c4 x?tal c3
lc865632/28/24/20/16/12/08a 18/20 < reset time and oscillation stabilizing time. > < hold release signal and oscillation stabilizing time. > figure 3 oscillation stable time power supply res interrnal rc resonator oscillation cf1, cf2 operation mode vdd vdd limit ov reset time tmscf unfixed reset instruction execution mode hold release signal interrnal rc resonator oscillation xt1, xt2 operation mode valid tmscf hold instruction execution mode xt1, xt2 cf1, cf2 tssxtal tssxtal
lc865632/28/24/20/16/12/08a 19/20 figure 4 reset circuit figure 5 serial input / output test condition figure 6 pulse input timing condition (note) fix the value of cres, rres that is sure to reset until 200 s, after power supply has been over inferior limit of supply voltage. c res vdd r res res so0, so1 sb0, sb1 si0 si1 sck0 sck1 tc k o tc ki t i c k tc kh tc kl tc k c y 0.5vdd 50pf 1k ?
lc865632/28/24/20/16/12/08a 20/20 memo: ps

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